1. Field of the Invention
The present invention generally relates to the field of analog-to-digital (A/D) converters. More specifically, the present invention relates to ramp generators utilized in A/D converters.
2. Description of the Related Art
A/D converters are utilized to represent analog signals in a digital form. A/D converters are typically employed in systems such as microcomputers, imaging systems, and automobile electronic systems. The analog information input to an A/D converter may be, for example, analog photocell charges from an image sensing device or measurements of physical variables such as temperature, force, etc. After an A/D converter converts the analog information to digital, the digital information can be stored in memory units and/or passed to processing circuits such as an image compression module.
A/D converters typically consist of active and passive devices among one of which is a "ramp generator". Ramp generators generate ramp-like signals that are monotonically increasing with time. FIG. 1(a) is a diagram of a conventional ramp generator. FIG. 1(a) shows a ramp generator 100 using a series of binary weighted capacitors, C.sub.1, C.sub.2, C.sub.3. . . C.sub.n, whereby C.sub.2 =2*C.sub.1, C.sub.3 =4*C.sub.1, etc. such that C.sub.n =2.sup.(.sup.n-1) *C.sub.1. Capacitors C.sub.1, C.sub.2, C.sub.3. . . C.sub.n act to provide charge to output node n.sub.OUT. Output node n.sub.OUT or a buffered version of output node n.sub.OUT forms the output of ramp generator 100. When the outputs of the n-bit counter transition high its associated capacitor (C.sub.1. . . C.sub.n) will add charge to node n.sub.OUT thus increasing its voltage. Conversely when an output of the counter transitions low it will subtract charge from n.sub.OUT thus decreasing its voltage. For an n-bit digital input signal IN from counter 110, the most significant bit n-1 will control a capacitor C.sub.n with a value of 2.sup.(n-1) *C.sub.1 and the least significant bit 0 will control the capacitor C.sub.1. In general, a bit k output by counter 110 will control a capacitor C.sub.K+1 with a value 2.sup.(n-1) *C.sub.1. Ramp generator 100 will ramp its output with each increment of counter 110.
Ramp generator 100 operates as follows. The output of the ramp generator, V.sub.RAMP is initialized to the desired starting value provided by the signal INITIAL.sub.-- VALUE, by asserting an INITIALIZE signal, which closes a switch SW. The voltage across capacitor, C.sub.1, C.sub.2 . . . C.sub.n, is initially equal to INITIAL.sub.-- VALUE since the counter begins at a value (n zeroes) (i.e., 0 volts). When the counter 110 is first incremented from an all-zero initial value, bit 0 will first go high as such charge is added to the output node. The added charge .DELTA.Q=C.sub.1 *V.sub.DD, where V.sub.DD is the voltage level appearing at the output of bit 0 of the counter resulting from the counter bit 0 to 1 transition. At this counter value of 1, all other bits 1 . . . n-1 will be zero. When the counter increments again (from 000 . . . 01 to 000 . . . 10), bit 0 will go low and bit 1 will be high. Thus, the capacitor C.sub.1 subtracts charge from node n.sub.OUT =C.sub.1 *V.sub.DD. But, since bit 1 is high, the capacitor C.sub.2 will add charge .DELTA.Q.sub.2 =C.sub.2 *V.sub.DD, where V.sub.DD is the voltage level appearing at bit 1 of the counter as a result of the bit 1 going high. Since C.sub.2 =2*C.sub.1, .DELTA.Q.sub.2 =2*C.sub.1 *.DELTA.V=2*.DELTA.Q.sub.1. The counter incrementing from 1 to 2 caused an extra .DELTA.Q.sub.1 amount of charge to appear at the output node. As the counter increases with time, either an extra bit will be turned high or some bits turned high and others turned low, so that in effect, charge that was previously contributed "subtracted" or discharged in favor of a greater charge amount.
The linear ramp output generated by the ramp generator of FIG. 1(a) is shown in FIG. 1(b). The ramps of FIG. 1(b) is an ideal ramp assuming no fluctuations in the amount of charge added to the output node, but is always a monotone increasing function of time.
The design of the conventional ramp generator shown in connection with FIG. 1(a) has several drawbacks. One drawback is that since the output of the ramp depends upon capacitors which should have matched values since each capacitor is presumed to be double (binary weighted) its predecessor. Furthermore, the conventional ramp generator occupies a lot of space since it uses a plurality of analog capacitors which in a digital system implies a misfit mixing of analog and digital process technology. Further, an n-bit counter requires n capacitors to generate the ramp, and thus may prohibit implementing large counters. Moreover, from a power perspective, the conventional ramp generator is inefficient and consumes a lot of power. As the ramp generator counts up, it adds charge, but also subtracts charge in some instances. For instance, when counter 110 counts from 1 (000.01) to 2 (000.10), capacitor C.sub.1 subtracts charge while capacitor C.sub.2 adds charge. The charge and voltage utilized by counter value 1 is useless and discarded at counter value 2. Every time charge is subtracted or dissipated, power is wasted.
Thus, there is a need for a ramp generator that utilizes less power and that can be implemented using fewer, less space-taking and more process efficient components than the ramp generator of the conventional design.